SHIFT REGISTERS
Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple bits of data, we need multiple flip flops.
Register is a device which is used to store such information. It is a group of flip flops connected in series used to store multiple bits of data.
Shift Register is a group of flip flops used to store multiple bits of data.
If the register is capable of shifting bits either towards right hand side or towards left hand side is known as shift register.
TYPES OF SHIFT REGISTER
Following are the four types of shift registers based on applying inputs and accessing of outputs.
- Serial In − Serial Out shift register (SISO)
- Serial In − Parallel Out shift register (SIPO)
- Parallel In − Serial Out shift register (PISO)
- Parallel In − Parallel Out shift register (PIPO)
Types
Serial-in to Parallel-out (SIPO)
the register is loaded with serial data, one bit at a time, with the stored data being available at the output in parallel form.
Serial-in to Serial-out (SISO)
the data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or right direction under clock control.
Parallel-in to Serial-out (PISO)
the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.
Parallel-in to Parallel-out (PIPO)
the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.
SISO SHIFT REGISTER
Serial-in, serial-out shift registers delay data by one clock time for each stage.
They will store a bit of data for each register.
A serial-in, serial-out shift register may be one to 64 bits in length, longer if registers or packages are cascaded.
Serial input serial output (serial shift right) register shift the data bit from left to right by 1 position per clock cycle.
Serial input serial output (serial shift left) register shift the datafrom right to left by 1 position per clock.
Working of SISO shift register
The shift register, which allows serial input (one bit after the other through a single data line) and produces a serial output is known as Serial-In Serial-Out shift register.
Since there is only one output, the data leaves the shift register one bit at a time in a serial pattern, thus the name Serial-In Serial-Out Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of four D flip-flops which are connected in a serial manner.
All these flip-flops are synchronous with each other since the same clock signal is applied to each flip flop.
The above circuit is an example of shift right register, taking the serial data input from the left side of the flip flop. The main use of a SISO is to act as a delay element.
Working of Serial-in to Parallel-out (SIPO) Shift Register
As shown in the above fig 4 stages are there as stage a having QA output, stage B having QB and like that, data in and clock this are the two inputs and data out is the output.
A serial-in, parallel-out shift register is similar to the serial-in, serial out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin.
It is different in that it makes all the internal stages available as outputs. Therefore, a serial-in, parallel-out shift register converts data from serial format to parallel format.
Also, the directional movement of the data through a shift register can be either to the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same register thereby making it bidirectional.
In this tutorial it is assumed that all the data shifts to the right, (right shifting).
The shift register, which allows serial input (one bit after the other through a single data line) and produces a parallel output is known as Serial-In Parallel-Out shift register.
The logic circuit given above shows a serial-in-parallel-out shift register.
The circuit consists of four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock signal to all the 4 flip flops in order to RESET them.
The output of the first flip flop is connected to the input of the next flip flop and so on.
All these flip-flops are synchronous with each other since the same clock signal is applied to each flip flop.
The above circuit is an example of shift right register, taking the serial data input from the left side of the flip flop and producing a parallel output.
Parallel-In Serial-Out Shift Register (PISO)
The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists of four D flip-flops which are connected.
The output of the previous flip flop and parallel data input are connected to the input of the MUX and the output of MUX is connected to the next flip flop.
All these flip-flops are synchronous with each other since the same clock signal is applied to each flip flop.
A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.
They are used in communication lines where de multiplexing of a data line into several parallel lines is required because the main use of the SIPO register is to convert serial data into parallel data.
Parallel-In Parallel-Out Shift Register (PIPO)
In this type of register, there are no interconnections between the individual flip-flops since no serial shifting of the data is required.
Data is given as input separately for each flip flop and in the same way, output also collected individually from each flip flop.
A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like SISO Shift register it acts as a delay element.
Applications of shift Registers
The shift registers are used for temporary data storage.
The shift registers are also used for data transfer and data manipulation.
The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time delay to digital circuits.
The serial-in parallel-out shift register is used to convert serial data into parallel data .
They are used in communication lines where de multiplexing of a data line into several parallel line is required.
A Parallel in Serial out shift register us used to convert parallel data to serial data.
Twisted ring counter or Johnson counter.
For multiplication and division.
Ring Counter.
Counter
Shift Register Counter
Shift Register Counters are the shift registers in which the outputs are connected back to the inputs in order to produce particular sequences.
Ring Counter
A ring counter is basically a shift register counter in which the output of the first flip flop is connected to the next flip flop and so on and the output of the last flip flop is again fed back to the input of the first flip flop, thus the name ring counter.
The data pattern within the shift register will circulate as long as clock pulses are applied.
The logic circuit given below shows a Ring Counter. The circuit consists of four D flip-flops which are connected. Since the circuit consists of four flip flops the data pattern will repeat after every four clock pulses as shown in the truth table below
Clock pulse-Q1-Q2-Q3-4
0 |1 | 0 | 0 | 1
1 |1 | 1 | 0 | 0
2|0 | 1 | 1 | 0
3|0 | 0 | 1 | 1
A Ring counter is generally used because it is self-decoding. No extra decoding circuit is needed to determine what state the counter is in.
In this way can design 4-bit Ring Counter using four D flip-flops. It is also known as One hot Counter.
In this counter, the output of the last flip-flop is connected to the input of the first flip-flip.
The main point of this Counter is that it circulates a single one (or zero) bit around the ring.
Ring counter is almost same as the shift counter.
The only change is that the output of the last flip-flop is connected to the input of the first flip-flop in case of ring counter but in case of shift resister it is taken as output. Except this all the other things are same.
No. of states in Ring counter = No. of flip-flop used
So, for designing 4-bit Ring counter we need 4 flip-flop Ring counter is a typical application of Shift registers.
In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flop simultaneously. Therefore, it is a Synchronous Counter.
Also, here we use Overriding input (ORI) to each flip-flop. Preset (PR) and Clear (CLR) are used as ORI.
Working of counters
When PR is 0, then the output is 1. And when CLR is 0, then the output is 0. Both PR and CLR are active low signal that is always works in value 0.
PR = 0, Q = 1 CLR = 0, Q = 0
These two values are always fixed. They are independent with the value of input D and the Clock pulse (CLK).
Here, ORI is connected to Preset (PR) in FF-0 and it is connected to Clear (CLR) in FF-1, FF-2, and FF-3.
Thus, output Q = 1 is generated at FF-0 and rest of the flip-flop generate output Q = 0. This output Q = 1 at FF-0 is known as Pre-set 1 which is used to form the ring in the Ring Counter.
This Pre seted 1 is generated by making ORI low and that time Clock (CLK) becomes don’t care.
After that ORI made to high and apply low clock pulse signal as the Clock (CLK) is negative edge triggered.
After that, at each clock pulse the preseted 1 is shifted to the next flip-flop and thus form Ring.
From the above table, we can say that there are 4 states in 4-bit Ring Counter.
4 states are:
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
Synchronous & Asynchronous Counter
Synchronous Counter
The synchronous counter, also known as parallel counter is the one in which each constituting flip flops are clocked with the same clock input simultaneously.
Basically, in the synchronous counter, all the flip flops in the cascade connection are individually connected to an external clock.
This facilitates the clocking of all the flip-flops constituting the counter at the same time instant with the same clock input.
This means the output of each flip flop varies in synchronization with the clock input.
So, due to this, the common clock signal causes the change in the state of each individual flip flop simultaneously. This resultantly leads to no ripple effect thus propagation delay does not exist in this counter.
Logic gates are used in synchronous counters to control the count sequence
Asynchronous Counter
In Asynchronous Counter is also known as Ripple Counter, different flip flops are triggered with different clock, not simultaneously.
It is also called Serial Counter.
Here the flip flops that constitute the counter are connected serially and the input clock pulse is provided to the first flip flop in the connection.
Here the clock input ripples through the counter as the output of the first flip flop generated due to the clock signal is further provided to adjacent flip flop in the forward direction.
The present output acts as the clock input for the next and so on. Due to this, in the asynchronous counter, the timing signal gets delayed by some amount on passing through each flip flop. Hence, this results in a propagation delay.
Differece between Synchronous counter & asynchronous counter
Synchronous counter
Also called : parallel counter.
Principle of operation : Each flip flop is triggered with same clock signal at the same time.
Decoding Errors: Not produced.
Operating Speed: Fast.
Design: complex.
Delay in signal propagation: very low.
Count sequence: Not Fixed.
Response to clock signal: Each flip-flop changes its state simultaneously.
Overall settling time: Maximum settling time out of the settling time of each flip flop in the configuration.
Flip-flop direct interconnection: Not Exist.
Applications: In moving machine controlling, alarms clocks, multiplexing circuits, etc.
Asynchronous counter
Also called: Serial Counter.
Principle of operation : Each flip flop is triggered with different clock signal at different instant of time.
Decoding Errors: produced.
Operating Speed : Comparatively slow.
Design : Simple.
Delay in signal propagation: Comparatively High
Count sequence : Fixed.
Response to clock signal: There is no simultaneous change in the state of all flip flops with change in clock input.
Overall settling time: Summation of settling time of each individual flip-flop.
Flip-flop direct interconnection: Exist.
Applications: In ring and johnson counters, frequency dividers, etc.
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